In a ring bus type multicore CPU for sharing one memory interface among multiple cores, accesses to a main memory are concentrated. In the normal operation, each CPU core has a cache, respectively, to read data actually from a shared main memory. Instead of reading of data from one main memory, it is considered a method of reading the data from cache data stored in each CPU core.
For example, a Read request is issued from a certain CPU core (called a “requester core”). In a conventional multicore structure, a main memory controller makes inquiries to the other CPU cores about the presence or absence of cache data instead of reading the data from the main memory. The CPU cores receiving the inquiries searches their caches for the data.
In a multicore operating environment, it is often the case that any of the CPU cores holds, in its cache, data of the same address as the main memory (called the address data). In this case, there is a conventional method in which the main memory controller issues an instruction to a requester core to transfer the cache content so that the data will be sent. However, this method takes time in proportion to the number of packed cores because inquiries to respective cores have to be made in order. Further, the inquiries to the respective CPU cores suffer from a high load placed on the main memory controller.
The following will describe snooping for coherence to ensure the coherency of data held in each cache in a structure of multiple CPU cores. In a multiprocessor equipped with cache memories, the coherency of data used in processing among multiple processors needs to be maintained. Bus snooping is often employed to maintain the coherency of data in conventional processors. Bus snooping is a function to watch transactions on a memory interface bus shared among respective processors and detect whether a transaction related to data in a cache memory allocated to each processor occurs.
When a transaction related to data in the cache memory allocated to a specific processor occurs, the processor updates a corresponding entry in the cache memory. Each of the other processors is notified of this update by snooping to set a dirty flag for the data stored in its cache so that the data will not be used, thus managing data in the entire multiprocessor system.
Japanese Patent Application Publication No. 2006-244460 provides a processor equipped with a cache memory capable of keeping the coherency of data among processors with excellent operational efficiency in a multiprocessor system. However, Patent Document 1 describes a model in which multiple processor cores have a single cache, which is different from a model in which respective processor cores have respective caches.
Japanese Patent Application Publication No. 2009-176179 discloses a technique using multiple processor cores having respective caches to make effective use of cache data held in respective processor cores. This technique shows a processing method used when a processor core fetches data from a main memory and a different processor core fetches the same memory data.